1. Field of the Invention
The present invention relates to a CDR (Clock Data Recovery) circuit provided with a hybrid-type PD (Phase Detector) implemented by a Hogge PD and an Alexander PD to serve as a circuit designed for an irregular NRZ signal and relates to a multiplied-frequency clock generation circuit adopting the same principle as the CDR circuit.
2. Description of the Related Art
FIG. 1 is a block diagram showing a CDR (Clock Data Recovery) circuit 10 provided with a Hogge PD (Phase Detector) to serve as a circuit designed for an irregular NRZ signal (refer to Hogge, CP: “A Self Correcting Clock Recovery Circuit,” Journal of Lightwave Technology, LT 3rd Volume, No. 6, December 1985, pp. 1312-1314).
As shown in the block diagram, the CDR circuit 10 employs a Hogge PD 11, a first CP (Charge Pump) 12, a second CP13, an LP (Loop Filter) 14 and a VCO (Voltage-controlled Oscillator) 15.
The Hogge PD 11 has a first DFF (D Flip-Flop) 11a for latching input data IDT, which is irregular NRZ data, with a timing determined by an eye-center clock signal ECCK. The Hogge PD 11 also has a second DFF 11b for latching Q1, which serves as the output of the first DFF 11a, with a timing determined by an eye-edge clock signal ECCK having a phase opposite to that of the eye-center clock signal ECCK.
In addition, the Hogge PD 11 also has a first EXOR (exclusive logical OR circuit) 11c for detecting a state of logical mismatching between the input data IDT and the output Q1 which serves as the output of the second DFF 11. On top of that, the Hogge PD 11 also has a second EXOR 11d for detecting a state of logical mismatching between the output Q1 and a signal Q2 which serves as the output of the second DFF 12.
In addition, the Hogge PD 11 also has a buffer 11e for delaying a clock signal CLK generated by the VCO 15 and supplying the delayed clock signal to the first DFF 11a as the eye-center clock signal ECCK. On top of that, the Hogge PD 11 also has an inverter 11f for inverting the clock signal CLK generated by the VCO 15 and supplying the inverted clock signal to the second DFF 11b as the eye-edge clock signal EECK.
A signal output by the first EXOR 11c serves as an up signal UP for driving the first charge pump (CP+) 12 to electrically charge the LF 14 with a current which is also referred to hereafter as an electrical charging current. On the other hand, a signal output by the second EXOR 11d serves as a down signal DOWN for driving the second charge pump (CP−) 13 to electrically discharge a current from the LF 14. In the following description, the current discharged by the second charge pump (CP−) 13 from the LF 14 is referred to as an electrical discharging current.
The LF 14 is a component for integrating and smoothing the electrical charging current supplied to the LF 14 by the first charge pump (CP+) 12 and the electrical discharging current drawn from the LF 14 by the second charge pump (CP−) 13 in order to generate an input signal to be fed to the VCO 15.
The VCO 15 is a component for generating the aforementioned clock signal CLK with a frequency according to the voltage of the input signal received from the LF 14. The clock signal CLK generated by the VCO 15 serves as a recovered clock signal RCCK output by the CDR circuit 10. On the other hand, the output Q1 generated by the first DFF 11a serves as retimed data RTDT output by the Hogge PD 11.
FIG. 2 is a timing diagram showing timing charts of operations carried out by the Hogge PD 11.
As shown in the timing diagram, the up signal UP generated by the first EXOR 11c is sustained at a high level during a period between times t1 and t2. The time t1 is a time at which the level of the input data IDT is changed. As described above, the input data IDT is irregular NRZ data. The time t2 is a time at which the eye-center clock signal ECCK rises, causing the first DFF 11a to latch the input data IDT and change the level of the output Q1 generated by the first DFF 11a. 
The period between the times t1 and t2 is the time delay of the eye-center clock signal ECCK relative to the change of the level of the input data IDT. That is to say, the period between the times t1 and t2 is an analog quantity representing the phase exhibited by the clock signal CLK output by the VCO 15 as a phase relative to the input data IDT.
The down signal DOWN generated by the second EXOR 11d is sustained at a high level during a period between the time t2 and a time t3. As described above, the time t2 is a time at which the level of the output Q1 is changed. The time t3 is a time at which the eye-edge clock signal EECK rises, causing the second DFF 11b to latch the output Q1 and change the level of the output Q2 generated by the second DFF 11b. 
The period between the times t2 and t3 is the pulse width (t3−t2) of the down signal DOWN and typically equal to half the period of the clock signal CLK generated by the VCO 15.
After the CDR feedback loop of the CDR circuit 10 has been settled in a steady state, the period of the electrical charging process carried out to supply an electrical charging current from the first charge pump (CP+) 12 to the loop filter 14 in accordance with the up signal UP is balanced on the average with the period of the electrical discharging process carried out to draw an electrical discharging current from the loop filter 14 to the second charge pump (CP−) 13 in accordance with the down signal DOWN.
Thus, if the absolute value of the magnitude of the electrical charging current supplied from the first charge pump (CP+) 12 to the loop filter 14 is equal to the absolute value of the magnitude of the electrical discharging current supplied from the loop filter 14 to the second charge pump (CP−) 13, the phase of the clock signal CLK generated by the VCO 15 is locked at an angle which makes the width of the high pulse of the up signal UP equal to the width of the high pulse of the down signal DOWN.
As a result, the width of the pulse of the up signal UP is equal to the width of the pulse of the down signal DOWN and, therefore, equal to half the period of the clock signal CLK generated by the VCO 15. That is to say, the phase of the clock signal CLK generated by the VCO 15 is locked upon the lapse of time equal to half the period of the clock signal CLK generated by the VCO 15 since the change of the level of the input data IDT. In other words, the phase of the clock signal CLK generated by the VCO 15 is locked at the middle of the irregular NRZ data.
In an actually manufactured integrated circuit, however, it is difficult to make the absolute value of the magnitude of the electrical charging current supplied from the first charge pump (CP+) 12 to the loop filter 14 perfectly equal to the absolute value of the magnitude of the electrical discharging current supplied from the loop filter 14 to the second charge pump (CP−) 13.
Let the absolute value of the magnitude of the electrical discharging current supplied from the loop filter 14 to the second charge pump (CP−) 13 be Ip. If the integrated circuit has asymmetrical characteristic in which the absolute value of the magnitude of the electrical charging current supplied from the first charge pump (CP+) 12 to the loop filter 14 is [Ip+Δi], the following description holds true.
In order to make the period of the electrical charging process carried out to supply an electrical charging current from the first charge pump (CP+) 12 to the loop filter 14 in accordance with the up signal UP balanced on the average with the period of the electrical discharging process carried out to draw an electrical discharging current from the loop filter 14 to the second charge pump (CP−) 13 in accordance with the down signal DOWN, as shown in a diagram of FIG. 3, the pulse width of the up signal UP has to be made shorter than the pulse width of the down signal DOWN by −ΔT.
It is to be noted that reference notation Tc shown in the diagram of FIG. 3 denotes the period of the clock signal CLK generated by the VCO 15.
Based on the fact that the size of an area representing the electrical charge supplied to the loop filter 14 in the electrical charging process in the diagram of FIG. 3 is equal to the size of an area representing the electrical charge drawn from the loop filter 14 in the electrical discharging process in the same diagram, the value of ΔT can be computed as follows.(Ip+Δi)(Tc/2−ΔT)=IpTc/2  (1)ΔT˜TcΔi/2Ip  (2)φE=2πΔT/Tc˜πΔi/Ip  (3)
FIG. 4 is a diagram showing a typical system configuration of a CDR feedback loop of the CDR circuit 10 which has the Hogge PD 11.
In the CDR feedback loop of the CDR circuit 10 having the Hogge PD 11, the eye-center clock signal ECCK has an equilibrium point at a position shifted from the center of each eye of the pattern composing the input data by ΔT which is approximated by Eq. (2).
In the CDR feedback loop shown in the system diagram of FIG. 4, the function of the Hogge PD 11 corresponds to subtraction to produce a steady-state phase error φE which is represented by Eq. (3).
In the system diagram of FIG. 4, reference notation Φ denotes the result of the Laplace transformation carried out on the phase φ of the input data IDT, reference notation Ω denotes the result of the Laplace transformation carried out on the angular frequency ω of the clock signal CLK generated by the VCO 15 and reference notation Θ denotes the result of the Laplace transformation carried out on the phase θ of the clock signal CLK.
In addition, reference notation Ip denotes the output current of the second charge pump (CP−) 13, reference notation N denotes the reciprocal of an average transition rate of the irregular NRZ data, symbol (R+1/sC) denotes the transfer function of the LF 14, which has a capacitor C and a resistor R connected in series to the capacitor C, whereas reference notation K denotes the sensitivity of the VCO 15. On top of that, reference notation φ E denotes a steady-state phase error caused by a difference in absolute magnitude between the electrical charging current supplied by the first charge pump (CP+) 12 to the LF 14 and the electrical discharging current drawn by the second charge pump (CP−) 13 from the LF 14.
The behavior of this loop system shows a quadratic response characteristic expressed by Eq. (4) which is given as follows.
                                                        Θ              +                              ϕ                ⁢                                                                  ⁢                E                                      Φ                    =                                                                      (                                                            s                      ⁢                                                                                          ⁢                      τ                                        +                    1                                    )                                ⁢                                  ω                  n                                            ⁢                                                                                                  s                2                            +                              2                ⁢                s                ⁢                                                                  ⁢                                  ζω                  n                                            +                              ω                n                2                                                    ⁢                                  ⁢                  τ          =          CR                ⁢                                  ⁢                              ω            n            2                    =                                    KIp              /              2                        ⁢            π            ⁢                                                  ⁢            NC                          ⁢                                  ⁢                  ζ          =                                    τω              n                        /            2                                              (        4        )            
In a steady state of the loop system shown in the diagram of FIG. 4 for φ=0, the angular frequency ω and the phase φ converge from their initial values to ω=0 and φ=−φE respectively without regard to the magnitudes of the initial values. These convergences of the angular frequency ω and the phase φ are shown as arrows along a locus on a phase-frequency plane in a diagram of FIG. 5.
On the assumption that the LF 14 and the VCO 15 are ideal and free of noises, in the CDR circuit 10 making use of the Hogge phase detector 11, the phase of the clock signal CLK generated by the VCO 15 does not fluctuate, being fixed at a point when the loop system is settled in a steady state. That is to say, when the loop system is settled in a steady state, no jitters are generated.
However, the convergence value of the phase φ is not 0, but −φE which is expressed by Eq. (3). As is obvious from Eq. (3), the convergence value of −φE is determined by a relative difference Δi/Ip between the electrical charging current supplied by the first charge pump (CP+) 12 to the LF 14 and the electrical discharging current drawn by the second charge pump (CP−) 13 from the LF 14. In addition, in a miniaturized integrated circuit, the relative difference Δi/Ip may exceed 0.2 in some cases. Thus, in such a case, the convergence value −φE becomes greater than 0.2π which is equal to 10% of the period of the clock signal CLK generated by the VCO 15.
The convergences in such a state much deteriorate the bearing force exhibited by the CDR circuit 10 as a force to receive a sudden phase change of the input data IDT in comparison with a case in which the phase □ converges to the ideal convergence value of 0. That is to say, the convergences in such a state much deteriorate the bearing force to receive input jitters.
FIG. 6 is a block diagram showing a CDR (Clock Data Recovery) circuit 10A which makes use of an Alexander PD (Phase Detector) 11A. For more information on this CDR circuit 10A, the reader is suggested to refer to Alexander, JDH: “Clock Recovery from Random Binary Signals,” Electronic Letters, 11th Volume, No. 32, Oct. 30, 1975, pp. 541-542.
In comparison with the Hogge PD 11 employed in the configuration of the CDR circuit 10 shown in the block diagram of FIG. 1, the Alexander PD 11A is provided additionally with a third DFF (D Flip-Flop) 11g and a fourth DFF 11h. 
In the Alexander PD 11A, the first EXOR 11c compares a value Q1 latched as a value of the input data IDT in the first DFF 11a with a timing determined by a specific eye-center clock signal ECCK to a value QE latched in the fourth DFF 11h with a timing determined by an eye-center clock signal ECCK immediately preceding the specific eye-center clock signal ECCK. The value QE latched in the fourth DFF 11h with a timing determined by the immediately preceding eye-center clock signal ECCK is a value that has been latched in the third DFF 11g with a timing determined by an eye-center clock signal ECCK appearing at a position in close proximity to an eye edge. If the comparison result produced by the first EXOR 11c indicates that the value Q1 latched with a timing determined by the specific eye-center clock signal ECCK does not match the value QE latched with a timing determined by the immediately preceding eye-center clock signal ECCK, the eye-edge clock signal EECK is determined to arrive before the eye edge. Thus, in this case, the first EXOR 11c employed in the Alexander PD 11A outputs the down signal DOWN in order to shift backward the too advanced phase of the clock signal CLK generated by the VCO 15.
On the other hand, the second EXOR 11d compares a value Q2 latched as a value of the input data IDT in the second DFF 11b with a timing determined by a particular eye-center clock signal ECCK to a value QE latched in the fourth DFF 11h with a timing determined by an eye-center clock signal ECCK immediately succeeding the particular eye-center clock signal ECCK. The value QE latched in the fourth DFF 11h with a timing determined by the immediately succeeding eye-center clock signal ECCK is a value that has been latched in the third DFF 11g with a timing determined by an eye-center clock signal ECCK appearing at a position in close proximity to an eye edge. If a comparison result produced by the second EXOR 11d indicates that the value Q2 latched with a timing determined by the particular eye-center clock signal ECCK does not match the value QE latched with a timing determined by the immediately succeeding eye-center clock signal ECCK, the eye-edge clock signal EECK is determined to arrive after the eye edge. Thus, in this case, the second EXOR 11d employed in the Alexander PD 11A outputs the up signal UP in order to shift forward the too retarded phase of the clock signal CLK generated by the VCO 15.
The up signal UP and the down signal DOWN are fed back to the VCO 15 by way of the first charge pump (CP+) 12 and the second charge pump (CP−) 13 respectively so that the phase of the eye-edge clock signal EECK is locked at a position in close proximity to the level-change point (or the eye edge) of the input data IDT whereas the phase of the eye-center clock signal ECCK is locked at a position in close proximity to the center of each eye of the pattern composing the input data IDT.
FIG. 7 is a timing diagram showing timing charts of operations carried out by the Alexander PD 11A.
The Alexander PD 11A is different from the Hogge PD 11 in that the Alexander PD 11A is not capable of outputting an analog quantity representing how much the phase of the clock signal CLK output by the VCO 15 lags behind or leads ahead of the input data IDT.
The Alexander PD 11A is characterized in that, even if there is a difference between the absolute value of the magnitude of the electrical charging current supplied from the first charge pump (CP+) 12 driven by the up signal UP to the loop filter 14 and the absolute value of the magnitude of the electrical discharging current supplied from the loop filter 14 to the second charge pump (CP−) 13 driven by the down signal DOWN, an angle at which the phase of the clock signal CLK output by the VCO 15 is to be locked hardly changes.
FIG. 8 is a diagram showing a typical system configuration of a CDR feedback loop of the CDR circuit 10A which has the Alexander PD 11A.
That is to say, the loop system making use of the Alexander PD 11A is expressed by a model which is shown in the diagram of FIG. 8. As shown in the figure, the Alexander PD 11A in the CDR feedback loop is represented by the three elements on the left side, i.e., a difference computing element, a quantization element and a delay element.
By the way, the CDR circuit 10A including the Alexander PD 11A is desired to employ a capacitor C which has a large capacitance. The capacitor C is used as a component for reducing the phase amplitude of a limit cycle vibration. That is to say, the capacitor C serves as a component for reducing jitters.
The capacitor C having a large capacitance is a hindrance to integration of the circuit employing the capacitor C. In addition, the capacitor C undesirably decreases the width of the response band of the clock signal CLK generated by the VCO 15 for changes of the phase of the input data IDT.
The decreased width of the response band of the clock signal CLK generated by the VCO 15 for changes of the phase of the input data IDT deteriorates the bearing force which is exhibited by the CDR circuit 10A as a force to deal with jitters. This is because the decreased width of the response band of the clock signal CLK generated by the VCO 15 means that the CDR circuit 10A is incapable of sufficiently coping with high-frequency components in the fluctuation of the phase of the input data IDT.
By the way, this invention specification refers to Japanese Patent No. 3,239,543.